August 25-27, 2013 at Stanford, Palo Alto, CA

Introduction

• Welcome from General Chairs
• Welcome from Program Chairs
• Mitsuo Saito Memorium
• Committees and Sponsors

Tutorials, August 25, 2013

Tutorial 1: Heterogeneous System Architecture (HSA): Overview and Implementation

Heterogeneous computing is emerging as a requirement for power-efficient SOC design: modern chips no longer rely on a single general-purpose processor, but instead benefit from specialized processors tailored for each task. Traditionally these specialized processors have been difficult to program due to separate memory spaces, kernel-driver-level interfaces, and specialized programming models. The Heterogeneous System Architecture (HSA) aims to bridge this gap by providing a common system architecture, and a basis for designing common higher-level programming models for all devices. This tutorial will bring in experts from member companies of the HSA Foundation to describe the Heterogeneous Systems Architecture and how it addresses the challenges of modern SOC devices.

• HSA Overview, Phil Rogers from AMD
• HSAIL Virtual Parallel ISA, Ben Sander from AMD
• HSA Memory Model, Benedict Gaster from Qualcomm
• HSA Queuing Model, Ian Bratt from ARM

Tutorial 2: Fast Storage for Big Data

Flash is emerging as a significant new storage technology for a wide range of storage requirements, spanning the industry from mobile devices to enterprise data centers. Its access time is 100X faster than traditional magnetic hard drives. However, exploitation of Flash is not straightforward as its physical characteristics introduce new requirements for the design of Flash-based storage components and fully integrated Flash-based storage systems. This tutorial will bring in experts from industry to talk about real systems,and the issues around exploiting flash memory technology in real system designs.

• Introduction, Tom McWilliams from Bay Storage Technology
• Flash’s Role in Big Data, Past Present, and Future, Jim Handy from Objective Analysis
• NAND Technology, Krishna Parat from Intel
• Delivering the Full Potential of PCIe Storage, Amber Huffman from Intel
• Systems Level Controller Design, Radoslav Danilak from Skyera
• Systems Case Study, Kevin Rowett from Violin Memory
• Flash in an Enterprise Storage Array: 10x Performance for Less Cost Than Disk, Neil Vachharajani from Pure Storage
• Flash Trends: Challenges and Future, John Davis from Microsoft Research
• Flash Adoption in the Enterprise, David Flynn from Primary Data

Conference Day 1, August 26, 2013

Session 1: SoC 1

• AMD’s Kabini APU SoC, Dan Bouvier, Ben Bates, Walter Fry and Sreekanth Godey from AMD
• XBOX One Silicon, John Sell and Pat O’Connor from Microsoft
• Clover Trail+ – Intel’s Next Atom SoC Smartphone Platform, Mark Ewert, Prakash Iyer and Waldo Bastian from Intel

Keynote 1

• The Chip Design Game at the End of Moore’s Law, Dr. Robert Colwell from DARPA

Session 2: Processors

• Next Generation POWER microprocessor, Jeff Stuecheli from IBM
• IBM zEC12 Processor Subsystem: The Foundation for a Highly Reliable, High Performance Mainframe Symmetric Multiprocessor System, Robert Sonnelitter from IBM

Keynote 2

• Google Glass, Babak Parviz from Google

Session 3: SoC 2

• AMD’s “Richland” Client APU SoC, Praveen Dongara, Lloyd Bircher and John Darilek from AMD
• A 50% Lower Power ARM Cortex CPU using DDC Transistors with Body Bias, David Kidd from SuVolta

Session 4: Interconnects

• Silicon Photonics Technology Platform for Integration of Optical IOs with ASICs, Peter De Dobbelaere from Luxtera
• NetSpeed eNoC – a Quantum Leap in On-Chip Interconnect Design, Sailesh Kumar from NetSpeed
• Integrating Rack Level Connectivity into a PCI Express Switch, Jack Regula from PLX Technology

Conference Day 2, August 27, 2013

Session 5: FPGA Based Dataflow

• Dataflow architectures for 10Gbps line-rate key-value-stores, Michaela Blott and Kees Vissers from Xilinx
• Going to the wire: The next generation financial risk management platform, Ari Studnitzer from CME Group and Oskar Mencer from Maxeler Technologies
• An FPGA-based In-line Accelerator for Memcached, Maysam Lavasani, Hari Angepat and Derek Chiou from University of Texas

Session 6: Networking

• Serial Networking Memory, Bandwidth Engine, Breaks 4.5 Billion Access per Second, Michael Miller from Mosys
• A 22nm High-Performance Flow Processor for 200Gb/s Software Defined Networking, Gavin Stark and Sakir Sezer from Netronome

Keynote 3

• Intellectual Property Issues in the Computer and Electronics Industries, Michael Brody, Vice-Chair, Intellectual Property from Winston and Strawn

Session 7: Mobility

• Qualcomm Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications, Lucian Codrescu, Willie Anderson, Suresh Venkumanhanti, Mao Zeng, Erich Plondke, Chris Koob, Ajay Ingle, Rick Maule and Raj Talluri from Qualcomm
• Power Management Challenges in Wireless WAN SoCs, Gunnar Bublitz from Intel
• 5th Generation Touchscreen Controller for Mobile Phones and Tablets, Milton Ribeiro and John Carey from Cypress

Session 8: Processors 2

• Hardware-level Thread Migration in a 110-core Shared-Memory Processor, Mieszko Lis, Keun Sup Shim, Brandon Cho, Ilia Lebedev and Srinivas Devadas from MIT
• Intel 4th Generation Core Processor (Haswell), Srinivas Chennupaty, Per Hammarlund and Stephan Jourdan from Intel
• Microprocessors for Roots of Trust, Kristopher Carver and Andras Moritz, Bluerisc

Session 9: Processors 3

• SPARC64 X+ : Fujitsu’s next generation processor for the UNIX servers,Toshio Yoshida from Fujitsu
• SPARC M6: Oracle’s Next Generation Processor for Massively Scalable Symmetric Multiprocessor (SMP) Data Center Servers with Enterprise Class RAS, Ali Vahidsafa and Sutikshan Bhutani from Oracle
• Bixby: the Scalability and Coherency Directory ASIC in Oracle’s M5/M6-32 Systems, Thomas Wicki and Jurgen Schulz from Oracle

Posters

• Winning Poster
• Measuring the Gap between Programmable and Fixed-Function Accelerators: A Case Study on Speech Recognition, Yunsup Lee, David Sheffield, Andrew Waterman, Michael Anderson, Kurt Keutzer and Krste Asanovic from UC Berkeley
• Finalist Posters
• What a Fast FPU Means for Algorithms: A Story of Vector Mathematical Functions, Marat Dukhan, College of Computing, Georgia Institute of Technology
• A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface, Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda and Hideharu Amano from Keio University; Ryuichi Sakamoto and Mitaro Namiki from Tokyo University of Agriculture and Technology; Kimiyoshi Usam from Shibaura Institute of Technology; Masaaki Kondo from University of Electro-Communications; Hiroshi Nakamura from The University of Tokyo, Japan
• Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping, Marco Ceriani and Gianluca Palermo from DEIB, Politecnico di Milano Milano, Italy; Simone Secchi from DIEE, Universita` di Cagliari Cagliari, Italy; Antonino Tumeo and Oreste Villa from Pacific Northwest National Laboratory Richland, WA, USA
• ESESC: A Fast Integrated Architectural Simulator, Ehsan K. Ardestani, Gabriel Southern, Jason Duong, Elnaz Ebrahimi and Jose Renau from UC Santa Cruz
• Automatic Number Plate Recognition System on an ARM-DSP and FPGA Heterogeneous SoC Platforms
  Zoe Jeffrey, Reza Sotudeh and Aladdin Ariyaeeinia from University of Hertfordshire, UK; Xiaojun Zhai from University of Essex; Faycal Bensaali from Qatar University
• The RISC-V Instruction Set, Andrew Waterman, Yunsup Lee, David Patterson and Krste Asanovic from UC Berkeley